Problems with wirebonding on probe marks and possible solutions

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 1350-1358

  Sauter, Wolfgang ^a   Aoki, Toyohiro ^a   Hisada, Takashi ^a   Miyai, Hirumitsu ^a   Petrarca, Kevin ^a   Beaulieu, Frederic ^a   Allard, Stephanie ^a   Power, Jennifer ^a   Agbesi, Michael ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; GOLD ALLOYS; INTEGRATED CIRCUIT TESTING; INTERMETALLICS; MICROPROCESSOR CHIPS; VLSI CIRCUITS; WIRE; YIELD STRESS;

BALL BOND; FINE PITCH WIREBOND; PROBE MARKS; WIREBONDING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0037674395     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Greg Hotchkiss et al, "Effects of Probe Damage on Wirebond Integrity", Proc 51st Electronic Components and Technology Conference 2001 p.1175-1180 (IEEE cat n.01CH37220)
2. LSI announcement in EETimes http://www.eetimes.com/story/OEG20021025S0040
3. Harman, G. Wire Bonding in Microelectronics Materials, Processes, Reliability and Yield, MsGraw-Hill (New York, 1997), pp. 116-121.
4. G.G. Harman, C.E. Johnson, "Wire Bonding to Advanced Copper-Low-K Integrated Circuits, the Metal/Dielectric Stacks, and Materials Considerations," IMAPS Proceedings, 2001 IMAPS, Oct 09-11, 2001, Baltimore, Maryland, (01-NOV-2001)