Defining canonical-signed-digit number systems as arithmetic codes

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2002, Pages 1593-1597

  DeBrunner, Linda S ^a   DeBrunner, Victor E ^a   Bhogaraju, Deepak ^a  

^a UNIVERSITY OF OKLAHOMA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; ELECTRIC FILTERS; FIELD PROGRAMMABLE GATE ARRAYS; VLSI CIRCUITS;

ARITHMETIC CODES;

SIGNAL ENCODING;

EID: 0037629500     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. A. Avizienis, "Signed-digit number representation for fast parallel arithmetic," IRE Trans. Electron. Comp., vol. EC-10, pp. 289-400, 1961.
2. H. L. Garner, "Number systems and arithmetic," Advanced Computers, vol. 6, pp. 131-194, 1965.
3. Jeffrey O. Coleman and Arda Yurdakul, "Fractions in the Canonical-Signed-Digit Number System," 2001 Conf. On Information Sciences and Systems, March 2001.
4. th European Conf. On Circuit Theory and Design (ECCTD '01), Finland, August 2001.
5. Ian H. Witten; Radford M. Neal, and John G. Cleary, "Arithmetic Coding for Data Compression," Communications of the AC.M, vol. 30(6), pp. 520-540, June 1987.
6. th Annual Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, pp. 1237-1240, November 2001.
7. Linda S. DeBrunner, Victor E. DeBrunner, and Deepak Bhogaraju, "Using Variable Length 13-ary, Radix-4 CSD Coefficients to Achieve Low-Area Implementations of FIR Filters," Midwest International Symposium on Circuits and Systems, Tulsa, Oklahoma, August 2002.