Bitwidth aware global register allocation

Conference Record of the Annual ACM Symposium on Principles of Programming Languages

Volumn , Issue , 2003, Pages 85-96

  Tallam, Sriraman ^a   Gupta, Rajiv ^a  

^a University of Arizona   (United States)

Author keywords

Embedded applications; Minimal bitwidth; Packing interfering nodes; Subword data

Indexed keywords

ALGORITHMS; DATA FLOW ANALYSIS; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; PROGRAM COMPILERS; SHIFT REGISTERS;

EMBEDDED PROCESSORS;

COMPUTER SCIENCE;

EID: 0037629493     PISSN: 07308566     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/604131.604139     Document Type: Conference Paper

References (20)

1. P. Briggs, K.D. Cooper, and L. Torczon, "Improvements to graph coloring register allocation," ACM Transactions on Programming Languages and Systems (TOPLAS), 16(3):428-455, May 1994.
2. M. Budiu, M. Sakr, K. Walker, and S.C. Goldstein, "BitValue Inference: Detecting and Exploiting Narrow Width Computations," 6th European Conference on Parallel Computing (Euro-Par), August 2000.
3. G. J. Chaitin, "Register allocation and spilling via graph coloring," SIGPLAN Symposium on Compiler Construction, June 1982.
4. J. Davidson and S. Jinturkar, "Memory access coalescing : a technique for eliminating redundant memory accesses," ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pages 186-195, 1994.
5. R.J. Fisher and H.G. Dietz, "Compiling for SIMD within Register," 11th International Workshop on Languages and Compilers for Parallel Computing (LCPC), LNCS, Springer Verlag, Chapel Hill, NC, August 1998.
6. J. Fridman, "Data Alignment for Sub-Word Parallelism in DSP," IEEE Workshop on Signal Processing Systems (SiPS), pages 251-260, 1999.
7. M.R. Garey and D.S. Johnson, Computers and intractability: a guide to the theory of NP-completeness, 1979.
8. L. George and A.W. Appel, "Iterated register coalescing," ACM Transactions on Programming Languages and Systems (TOPLAS), 18(3):300-324, May 1996.
9. R. Gupta, E. Mehofer, and Y. Zhang, "A Representation for Bit Section Based Analysis and Optimization," International Conference on Compiler Construction (CC), LNCS 2304, Springer Verlag, pages 62-77, Grenoble, France, April 2002.
10. A. Koseki, H. Komatsu, and T. Nakatani, "Preference-Directed Graph Coloring," ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pages 33-44, June 2002.
11. S. Larsen and S. Amarasinghe, "Exploiting Superword Level Parallelism with Multimedia Instruction Sets," ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pages 145-156, Vancouver B.C., Canada, June 2000.
12. C. Lee, M. Potkonjak, and W.H. Mangione-Smith, "Mediabench: a tool for evaluating and synthesizing multimedia and communications systems," IEEE/ACM International Symposium on Microarchitecture (MICRO), Research Triangle Park, North Carolina, December 1997.
13. B. Li and R. Gupta, "Bit section instruction set extension of ARM for embedded applications," International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES), Grenoble, Oct. 2002.
14. G. Memik, B. Mangione-Smith, and W. Hu, "NetBench: A Benchmarking Suite for Network Processors," IEEE International Conference Computer-Aided Design (ICCAD), Nov. 2001.
15. X. Nie, L. Gazsi, F. Engel, and G. Fettweis, "A New Network Processor Architecture for High Speed Communications," IEEE Workshop on Signal Processing Systems (SiPS), pages 548-557, 1999.
16. D. Seal, Editor, "ARM architecture reference manual," Second Addition, Addison-Wesley.
17. M. Stephenson, J. Babb, and S. Amarasinghe, "Bitwidth Analysis with Application to Silicon Compilation," ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pages 108-120, Vancouver B.C., Canada, June 2000.
18. J. Wagner and R. Leupers, "C Compiler Design for an Industrial Network Processor," ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES), pages 155-164, June 2001.
19. T. Wolf and M. Franklin, "Commbench - a telecommunications benchmark for network processors," IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2000.
20. Y. Zhang and R. Gupta, "Data Compression Transformations for Dynamically Allocated Data Structures," International Conference on Compiler Construction (CC), LNCS 2304, Springer Verlag, pages 14-28, Grenoble, France, April 2002.