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Volumn 1, Issue , 2003, Pages

A high-resolution and fast-conversion time-to-digital converter

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; PHASE SHIFT; TIMING CIRCUITS;

EID: 0037483035     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (7)

References (10)
  • 2
    • 0030168854 scopus 로고    scopus 로고
    • A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip
    • Jun.
    • Santos D.M. "A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip", IEEE Trans. on Nuclear Science, vol. 43, pp. 1717-1719, Jun. 1996.
    • (1996) IEEE Trans. on Nuclear Science , vol.43 , pp. 1717-1719
    • Santos, D.M.1
  • 3
    • 0027642572 scopus 로고
    • The use of stabilized CMOS delay line for the digitization of short time intervals
    • Aug.
    • Rahkonen T. and Ksotamovaara J. "The use of stabilized CMOS delay line for the digitization of short time intervals" IEEE J. Solid-State Circuits,vol. 28, pp. 887-894, Aug. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , pp. 887-894
    • Rahkonen, T.1    Ksotamovaara, J.2
  • 5
    • 17144435893 scopus 로고    scopus 로고
    • A high resolution CMOS time-to-digital converter utilizing a vernier delay line
    • Feb.
    • Dudek P., Szczepanski S. and Hatfield J.V. "A high resolution CMOS time-to-digital converter utilizing a vernier delay line" IEEE J. Solid-State Circuits, vol. 35, pp. 240-247, Feb. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , pp. 240-247
    • Dudek, P.1    Szczepanski, S.2    Hatfield, J.V.3
  • 6
    • 0028388471 scopus 로고
    • A sampling technique and its CMOS implementation with 1Gb/s bandwidth and 25ps resolution
    • Mar.
    • Gray C.T., Liu W.T., Noije W., Hughes T., and Cavin III R.K. "A sampling technique and its CMOS implementation with 1Gb/s bandwidth and 25ps resolution" IEEE J. Solid-State Circuits, vol. 29, pp. 340-349, Mar. 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , pp. 340-349
    • Gray, C.T.1    Liu, W.T.2    Noije, W.3    Hughes, T.4    Cavin R.K. III5
  • 7
    • 0030193242 scopus 로고    scopus 로고
    • An integrated high resolution CMOS timing generator based on an array of delay locked loops
    • Jul.
    • Christiansen J. "An integrated high resolution CMOS timing generator based on an array of delay locked loops" IEEE J. Solid-State Circuits, vol. 31, pp. 952-957, Jul. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , pp. 952-957
    • Christiansen, J.1
  • 10
    • 0029408024 scopus 로고
    • Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter
    • November
    • Novof I., Austin, J, Kelker R, Strayer D. and Wyatt S. "Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter" IEEE J. Solid-State Circuits, vol. 30, pp. 1259-1266, November 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , pp. 1259-1266
    • Novof, I.1    Austin, J.2    Kelker, R.3    Strayer, D.4    Wyatt, S.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.