Practical compact modeling approaches and options for sub-0.1 μm CMOS technologies

Microelectronics Reliability

Volumn 43, Issue 3, 2003, Pages 399-404

  Chan, Mansun ^a,b   Xi, Xuemei ^a   He, Jin ^a   Cao, Kanyu M ^a   Dunga, Mohan V ^a   Niknejad, Ali M ^a   Ko, Ping K ^b   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; MOSFET DEVICES; STANDARDIZATION;

CHARGE-BASED MODELS; CONDUCTANCE-BASED MODELS; SURFACE-POTENTIAL BASED MODELS;

CMOS INTEGRATED CIRCUITS;

EID: 0037371968     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(02)00278-0     Document Type: Conference Paper

References (9)

1. 〈http://www.eigroup.org/cmc〉.
2. 〈.http://www-device.eecs.berkeley.edu/̃bsim3〉.
3. Meyer J.E. MOS models and circuit simulation. RCA Rev. 32:1971;42-63.
4. Pao H.C., Sah C.T. Effects of diffusion current on characteristics of metal-oxide-(insulator)-semiconductor transistors. Solid-State Electron. 9:1966;927-937.
5. 〈.http://www.semiconductors.philips.com/Philips_Model〉.
6. Miura-Mattausch M., Jacobs H. Analytical model for circuit simulation with quarter micron metal oxide semiconductor field effect transistors: subthreshold characteristics. Jpn. J. Appl. Phys. 29:1990;L2279-L2282.
7. Enz C.C., Krummenacher F., Vittoz E.A. An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage design and simulation. Low-Voltage Low-Power Des. 8:1995;83-114.
8. Sheu B.J., Scharfetter D.L., Ko P.K., Jeng M.C. BSIM: berkeley short channel IGFET model for MOS transistors. IEEE J. Solid-State Circ. SC-22(4):1987;558-566.
9. 〈http://www-device.eecs.berkeley.edu/̃ptm〉.