Reverse-order-restoration-based static test compaction for synchronous sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 3, 2003, Pages 293-304

  Guo, Ruifeng ^a,b   Reddy, Sudhakar M ^a   Pomeranz, Irith ^c  

^a IA United States   (United States)

^b INTEL CORPORATION   (United States)

^c PURDUE UNIVERSITY   (United States)

Author keywords

Sequential circuits; Static compaction; Test sequence compaction

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; VECTORS;

REVERSE ORDER RESTORATION; STATIC TEST SEQUENCE COMPACTION; VECTOR RESTORATION PROCESS;

SEQUENTIAL CIRCUITS;

EID: 0037343523     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.807885     Document Type: Article

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