Deep levels in ion implanted field effect transistors on SiC

Solid-State Electronics

Volumn 47, Issue 2, 2003, Pages 193-198

  Mitra, S ^a   Rao, Mulpury V ^a   Jones, K ^b   Papanicolaou, N ^c   Wilson, S ^d  

^a George Mason University   (United States)

^b U S ARMY RESEARCH LABORATORY   (United States)

^c NAVAL RESEARCH LABORATORY   (United States)

^d MOTOROLA INC   (United States)

Author keywords

Annealing; Deep levels; DLTS; Ion implantation; MESFET; MISFET; SiC

Indexed keywords

ACTIVATION ENERGY; ANNEALING; DIELECTRIC MATERIALS; ELECTRON TRAPS; HOLE TRAPS; INTERFACES (MATERIALS); ION IMPLANTATION; SILICON CARBIDE;

CHANNEL MOBILITY;

MISFET DEVICES;

EID: 0037290372     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(02)00194-6     Document Type: Conference Paper

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