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Volumn 38, Issue 1, 2003, Pages 138-140

A 1.76-GHz 22.6-mW ΔΣ fractional-N frequency synthesizer

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; ELECTRIC POTENTIAL; FLIP FLOP CIRCUITS; FREQUENCY MODULATION; PHASE LOCKED LOOPS; RADIO RECEIVERS; VARIABLE FREQUENCY OSCILLATORS; WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 0037249335     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.806261     Document Type: Article
Times cited : (13)

References (12)
  • 3
    • 0003897255 scopus 로고
    • Frequency synthesizer having fractional frequency divider in phase-locked loop
    • U.S. Patent 3 959 737, May 25
    • W. J. Tanis, "Frequency Synthesizer Having Fractional Frequency Divider in Phase-Locked Loop," U.S. Patent 3 959 737, May 25, 1976.
    • (1976)
    • Tanis, W.J.1
  • 5
    • 0031332530 scopus 로고    scopus 로고
    • A 27-mW cmos fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation
    • Dec.
    • M. H. Perrott, T. L. Tewksbury III, and C. G. Sodini, "A 27-mW cmos fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation," IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , pp. 2048-2060
    • Perrott, M.H.1    Tewksbury T.L. III2    Sodini, C.G.3
  • 7
    • 0003645574 scopus 로고    scopus 로고
    • GSM technical specification: Digital cellular telecommunications system (Phase 2+); radio transmission and reception (GSM 05.05)
    • European Telecommunications Standards Institute (ETSI)
    • "GSM Technical Specification: Digital Cellular Telecommunications System (Phase 2+); Radio Transmission and Reception (GSM 05.05)," European Telecommunications Standards Institute (ETSI), 1996.
    • (1996)
  • 8
    • 0030188644 scopus 로고    scopus 로고
    • A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS
    • July
    • J. Craninckx and M. S. J. Steyaert, "A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS," IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , pp. 890-897
    • Craninckx, J.1    Steyaert, M.S.J.2
  • 10
    • 0029244247 scopus 로고
    • Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS
    • Feb.
    • B. Razavi, K. F. Lee, and R. H. Yan, "Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS," IEEE J. Solid-State Circuits, vol. 30, pp. 101-109, Feb. 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , pp. 101-109
    • Razavi, B.1    Lee, K.F.2    Yan, R.H.3
  • 11
    • 0028515930 scopus 로고
    • A sub-1 mA 1.5-GHz silicon bipolar dual modulus prescaler
    • Oct.
    • T. Seneff, L. McKay, K. Sakamoto, and N. Tracht, "A sub-1 mA 1.5-GHz silicon bipolar dual modulus prescaler," IEEE J. Solid-State Circuits, vol. 29, pp. 1206-1211, Oct. 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , pp. 1206-1211
    • Seneff, T.1    McKay, L.2    Sakamoto, K.3    Tracht, N.4
  • 12
    • 13444266779 scopus 로고    scopus 로고
    • A novel phase detector with no dead zone and a chargepump with very wide output voltage range
    • R. Ahola and K. Halonen, "A novel phase detector with no dead zone and a chargepump with very wide output voltage range," in Proc. ESSCIRC 1998, The Hague, The Netherlands, Sept. 1998, pp. 352-355.
    • Proc. ESSCIRC 1998, The Hague, The Netherlands, Sept. 1998 , pp. 352-355
    • Ahola, R.1    Halonen, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.