SCOPUS 정보 검색 플랫폼

International Journal of Production Research

Volumn 40, Issue 4, 2002, Pages 1017-1028

Cycle time estimation models for printed circuit board design

(3) Haberle, K R a Burke, R J a Graves, R J a

a RENSSELAER POLYTECHNIC INSTITUTE (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPETITION; DESIGN; ELECTRONICS INDUSTRY; ESTIMATION; INTEGRATED CIRCUIT LAYOUT; INTERNATIONAL TRADE; MANUFACTURE; MATHEMATICAL MODELS; PRINTED CIRCUIT MANUFACTURE; PRODUCT DEVELOPMENT; PRODUCTION ENGINEERING;

CYCLE TIME ESTIMATION MODEL; PRINTED CIRCUIT BOARD ASSEMBLIES; PRINTED CIRCUIT BOARD DESIGN;

PRINTED CIRCUIT BOARDS;

EID: 0037051309 PISSN: 00207543 EISSN: None Source Type: Journal
DOI: 10.1080/00207540110097680 Document Type: Article

Times cited : (5)

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