Automatic large-scale integrated circuit synthesis using allocation-based scheduling algorithm

Microprocessors and Microsystems

Volumn 26, Issue 3, 2002, Pages 139-147

  Papa, Gregor ^a   Šilc, Jurij ^a  

^a JO EF STEFAN INSTITUTE   (Slovenia)

Author keywords

Automatic circuit design; Evolutionary computation; High level synthesis; Scheduling and allocation

Indexed keywords

AUTOMATION; EVOLUTIONARY ALGORITHMS; LOGIC CIRCUITS; LOGIC DESIGN; OPTIMIZATION; RESOURCE ALLOCATION; SCHEDULING;

AUTOMATIC CIRCUIT DESIGN; REGISTER-TRANSFER LEVEL (RTL);

INTEGRATED CIRCUIT LAYOUT;

EID: 0037029240     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0141-9331(02)00008-X     Document Type: Article

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10. Scheduling strategies in high level synthesis
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