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Volumn 49, Issue 12, 2002, Pages 2279-2287

Active devices under CMOS I/O pads

Author keywords

CMOS; Copper; ESD; FSG; I O bonding pad; IMD; Low k; Propagation gate delay; Ring oscillator; Second break down trigger point; SOC; Transmission line pulse

Indexed keywords

COPPER; CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; ELECTRIC DISCHARGES; ELECTRIC EQUIPMENT PROTECTION; ELECTRIC IMPEDANCE; ELECTROSTATIC DEVICES; GLASS; OSCILLATORS (ELECTRONIC); STRESSES; THERMAL EFFECTS;

EID: 0036999720     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.807452     Document Type: Article
Times cited : (9)

References (13)
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  • 3
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    • Reliability of VLSI-level chip assembly for the development of back-end technologies using a test chip with a top two-level metal structure
    • K. Y. Chou, M. J. Chen, C.-W. Liu, and B.-H. Lin, "Reliability of VLSI-level chip assembly for the development of back-end technologies using a test chip with a top two-level metal structure," IEEE Trans. Device Mater. Reliab., vol. 2, pp. 50-59, 2002.
    • (2002) IEEE Trans. Device Mater. Reliab. , vol.2 , pp. 50-59
    • Chou, K.Y.1    Chen, M.J.2    Liu, C.-W.3    Lin, B.-H.4
  • 5
    • 0004245602 scopus 로고    scopus 로고
    • International technology roadmap for semiconductors (ITRS), 2001 edition
    • Semiconductor Industry Association; Apr.
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    • (2001)
  • 6
    • 0035397793 scopus 로고    scopus 로고
    • ESD protection under grounded-up bond pads in 0.13 μ m eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology
    • July
    • K. Y. Chou and M. J. Chen, "ESD protection under grounded-up bond pads in 0.13 μ m eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology," IEEE Electron Device Lett., vol. 22, pp. 342-344, July 2001.
    • (2001) IEEE Electron Device Lett. , vol.22 , pp. 342-344
    • Chou, K.Y.1    Chen, M.J.2
  • 7
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    • Active circuits under wire bonding I/O pads in 0.13 μ m eight-level Cu metal, FSG low-k inter-metal dielectric CMOS technology
    • ____, "Active circuits under wire bonding I/O pads in 0.13 μ m eight-level Cu metal, FSG low-k inter-metal dielectric CMOS technology," IEEE Electron Device Lett., vol. 22, pp. 466-468, 2001.
    • (2001) IEEE Electron Device Lett. , vol.22 , pp. 466-468
    • Chou, K.Y.1    Chen, M.J.2
  • 9
    • 0019689616 scopus 로고
    • A new integration technology that enables forming bonding pads on active areas
    • K. Mukai, A. Hiraiwa, S. Muramatsu, I. Yoshida, and S. Harada, "A new integration technology that enables forming bonding pads on active areas," in IEDM Tech. Dig., 1981, pp. 62-65.
    • (1981) IEDM Tech. Dig. , pp. 62-65
    • Mukai, K.1    Hiraiwa, A.2    Muramatsu, S.3    Yoshida, I.4    Harada, S.5
  • 13
    • 0033683693 scopus 로고    scopus 로고
    • Addressing ESD for microprocessors and ASIC's in 21st century technologies
    • A. Amerasekera, "Addressing ESD for microprocessors and ASIC's in 21st century technologies," in Symp. VLSI Circuits Dig. Tech., 2000, pp. 84-87.
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    • Amerasekera, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.