The 1/f1.7 noise in submicron SOI MOSFETs with 2.5 nm nitrided gate oxide

IEEE Transactions on Electron Devices

Volumn 49, Issue 12, 2002, Pages 2367-2370

  Lukyanchikova, Nataliya ^a   Petrichuk, Michail ^a   Garbar, Nikolay ^a   Simoen, Eddy ^b   Mercha, Abdelkarim ^b   Claeys, Cor ^b,c   Van Meer, Hans ^b,c   De Meyer, K ^b,c  

^a INSTITUTE OF SEMICONDUCTOR PHYSICS   (Ukraine)

^b IMEC   (Belgium)

^c Katholieke Universiteit Leuven   (Belgium)

Author keywords

1 f noise; Low frequency noise; SOI

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE;

GATE CURRENT; GATE VOLTAGE; LOW FREQUENCY NOISE; NITRIDED GATE OXIDE; POWER SPECTRAL DENSITY;

MOSFET DEVICES;

EID: 0036999666     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.807448     Document Type: Article

References (17)

1. Y.-C. Tseng, W. M. Huang, M. Mendicino, D. J. Monk, P. J. Welch, and J. C. S. Woo, "Comprehensive study on low-frequency noise characteristics in surface channel SOI CMOSFETs and device design optimization for RFICs," IEEE Trans. Electron Devices, vol. 48, pp. 1428-1437, July 2001.
2. W. Jin, P. C. H. Chan, S. K. H. Fung, and P. K. Ko, "Shot-noise-induced excess low-frequency noise in floating-body partially depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 46, pp. 1180-1185, June 1999.
3. G. O. Workman and J. G. Fossum, "Physical noise modeling of SOI MOSFETs with analysis of the Lorentzian component in the low-frequency noise spectrum," IEEE Trans. Electron Devices, vol. 47, pp. 1192-1201, June 2000.
4. S. Haendler, J. Jomaah, F. Balestra, J.L. Pelloie, and C. Raynaud, "Kink-related excess noise in deep submicron partially and moderately fully depleted unibond n-metal oxide semiconductor field effect transistor (MOSFET)," Jpn. J. Appl. Phys., vol. 39, no. 4B, pp. 2261-2263, April 2000.
5. J. Jomaah and F. Balestra, "Impact of the latch phenomenon on low-frequency noise in SOI MOSFETs," Microelectron. Reliab., vol. 38, no. 4, pp. 567-570, April 1998.
6. N. B. Lukyanchikova, M. V. Petrichuk, N. P. Garbar, E. Simoen, and C. Claeys, "Back and front interface related generation-recombination noise in buried-channel SOI pMOSFETs," IEEE Trans. Electron Devices, vol. 43, pp. 417-423, Mar. 1996.
7. D. S. Ang, Z. Lun, and C. H. Ling, "Generation-recombination noise in the near fully depleted SIMOX n-MOSFET operating in the linear regime," IEEE Electron Device Lett., vol. 22, pp. 545-547, Nov. 2001.
8. T. Ushiki, H. Ishino, and T. Ohmi, "Effect of starting SOI material quality on low-frequency noise characteristics in partially-depleted floating-body SOI MOSFETs," IEEE Electron Device Lett., vol. 21, pp. 610-612, Dec. 2000.
9. H. S. Momose, H. Kimijima, S. Ishizuka, Y. Miyahara, T. Ohguro, T. Yoshitomi, E. Morifuji, S. Nakamura, T. Morimoto, Y. Katsumata, and H. Iwai, "A study of flicker noise in n- and p-MOSFETs with ultra-thin oxide in the direct-tunneling regime," in IEDM Tech. Dig., Dec. 1998, pp. 923-926.
10. B. E. Weir, P. J. Silverman, D. Monroe, K. S. Krisch, M. A. Alam, G. B. Alers, T. W. Sorsch, G. L. Timp, F. Baumann, C. T. Liu, Y. Ma, and D. Hwang, "Ultra-thin gate dielectrics: They break down, but do they fail?," in IEDM Tech. Dig., Dec. 1997, pp. 73-76.
11. 1.7 noise in deep submicron partially depleted SOI transistors," in Proc. ESSDERC 2002, G. Baccarani, E. Gnani, and M. Rudan, Eds., Italy, 2002, pp. 75-78.
12. R. Jayaraman and C. G. Sodini, "A 1/f noise technique to extract the oxide trap density near the conduction band edge of silicon," IEEE Trans. Electron Devices, vol. 36, pp. 1773-1782, Sept. 1989.
13. K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, "A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors," IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 654-665, March 1990.
14. E. Simoen, M. Da Rold, C. Claeys, N. Lukyanchikova, M. Petrichuk, and N. Garbar, "Flicker noise in submicron MOSFETs with 3.5 nm nitrided gate oxide," in Proc. ICNF '2001, G. Bosman, Ed., Singapore, 2001, pp. 177-180.
15. +-polysilicon/oxide interface traps in ultrathin oxides," Electrochem. Solid-State Lett., vol. 4, no. 6, pp. G47-G49, June 2001.
16. 2 interface trap modeling," Solid-State. Electron., vol. 35, pp. 843-854, 1992.
17. E. Simoen and C. Claeys, "On the flicker noise in submicron silicon MOSFETs," Solid-State Electron., vol. 43, pp. 865-882, 1999.