A low-power 2.1 GHz 32-bit carry lookahead adder using dual path All-N-Logic

Midwest Symposium on Circuits and Systems

Volumn 2, Issue , 2002, Pages

  Yang, Ge ^a   Jung, Seong Ook ^a,b   Kim, Soo Hwan ^a   Kang, Sung Mo ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC NETWORK ANALYSIS; FREQUENCIES; LOGIC CIRCUITS; SIGNAL PROCESSING; TIMING CIRCUITS;

CLOCK SIGNALS;

ADDERS;

EID: 0036979469     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. N. F. Goncalves and H. J. De Man, "NORA: A race-free dynamic CMOS technology for pipelined logic structures," IEEE J. Solid-State Circuits, vol.18, pp. 261-266, June 1983.
2. C. M. Lee and E. W. Szeto, "Zipper CMOS," IEEE Circuits Devices Mag., pp. 10-16, May 1986.
3. J. Yuan and C. Svensson, "High-speed CMOS circuit technique," IEEE J. Solid-State Circuits, vol.24, pp. 62-70, Feb. 1989.
4. R. X. Gu and M. I. Elmasry, "All-N-logic high-speed true-single-phase dynamic CMOS logic," IEEE J. Solid-State Circuits, vol.31, pp. 221-229, Feb. 1996.
5. C.-C. Wang, P.-M. Lee, R.-C. Lee and C.-J. Huang, "A 1.25 GHz 32-bit tree-structured carry lookahead adder," 2001 IEEE Inter. Symp. on Circuits and Systems, Vol.4, pp. 80-83, 2001.
6. K.-H. Cheng, W.-S. Lee and Y.-C. Huang, "A 1.2V 500MHz 32-bit Carry-Lookahead Adder," The 8th IEEE International Conference on Electronics, Circuits and Systems, Vol. 2, pp. 765-768, 2001.
7. S. Knowles, "A family of adders," 15th IEEE Symposium on Computer Arithmetic, pp. 277-281, 2001.
8. P. M. Kogge and H. S. Stone, "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations," IEEE Trans., C-22(8):786-793, Aug. 1973.