A learnable cellular neural network structure with ratio memory for image processing

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 49, Issue 12, 2002, Pages 1713-1723

  Wu, Chung Yu ^a   Cheng, Chiu Hung ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Cellular neural network (CNN); Divider; Multiplier; Ratio memory (RM)

Indexed keywords

ASSOCIATIVE STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIVIDING CIRCUITS (ARITHMETIC); ELECTRIC CONVERTERS; ELECTRIC CURRENTS; INTEGRATED CIRCUIT LAYOUT; MULTIPLYING CIRCUITS; PATTERN RECOGNITION;

ASSOCIATIVE MEMORY; HEBBIAN LEARNING RULE; ON-CHIP LEARNING CIRCUIT; PATTERN LEARNING; RATIO MEMORY CELLULAR NEURAL NETWORK; SOFTWARE PACKAGE HSPICE; SOFTWARE PACKAGE MATLAB;

CELLULAR NEURAL NETWORKS;

EID: 0036963696     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2002.805697     Document Type: Article

References (21)

1. L. O. Chua and L. Yang, "Cellular neural networks: Theory," IEEE Trans. Circuits Syst., vol. 35, pp. 1257-1272, Oct. 1988.
2. ____, "Cellular neural networks: Applications," IEEE Trans. Circuits Syst., vol. 35, pp. 1273-1290, Oct. 1988.
3. T. Roska, "Analog events and a dual computing structure using analog and digital circuits and operators," in Discrete Event Systems: Models and Applications, P. Varaiya and A. B. Kurzhanski, Eds. New York: Springer-Verlag, 1988, pp. 225-238.
4. D. Liu and A. N. Michel, "Cellular neural networks for associative memories," IEEE Trans. Circuits Syst. II, vol. 40, pp. 119-121, Feb. 1993.
5. M. Brucoli, L. Carnimeo, and G. Grassi, "An approach to the design of space-varying cellular neural networks for associative memories," in Proc. 37th Midwest Symp. Circuits and Systems, vol. 1, 1994, pp. 549-552.
6. A. Lukianiuk, "Capacity of cellular neural networks as associative memories," in Proc. 4th IEEE Int. Workshop Cellular Neural Networks and Their Applications, 1996, pp. 37-40.
7. H. Kawabata, M. Nanba, and Z. Zhang, "On the associative memories in cellular neural networks," in Proc. IEEE Int. Conf. Systems, Man and Cybernetics, vol. 1, 1997, pp. 929-933.
8. P. Szolgay. I. Szatmari, and K. Laszlo, "A fast fiexed point learning method to implement associative memory on CNNs," IEEE Trans. Circuits Syst. I, vol. 44, pp. 362-366, Apr. 1997.
9. R. Perfetti and G. Costantini, "Multiplierless digital learning algorithm for cellular neural networks," IEEE Trans. Circuits Syst. I, vol. 48, pp. 630-635, May 2001.
10. A. Paasio, K. Halomen, and V. Porra, "CMOS implementation of associative memory using cellular neural network having adjustable template coefficients," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 6, 1994, pp. 487-490.
11. S. Grossberg, "Nonlinear difference-differential equations in prediction and learning theory," Proc. Nat. Acad. Sci. USA, vol. 58, pp. 1329-1334, 1967.
12. ____ The Adaptive Brain I: Cognition, Learning, Reinforcement and Rhythm. Amsterdam, North-Holland: Elsevier, 1986.
13. ____ The Adaptive Brain II: Vision, Speech, Language and Motor Control. Amsterdam, North-Holland: Elsevier, 1986.
14. C.-Y. Wu and J.-F. Lan, "CMOS current-mode neural associative memory design with on-chip learning," IEEE Trans. Neural Networks, vol. 7, pp. 167-181, Jan. 1996.
15. J.-F. Lan and C.-Y. Wu, "CMOS current-mode outstar neural networks with long-period analog ratio memory," in Proc. Int. Symp. Circuits and Systems, vol. 3, 1995, pp. 1676-1679.
16. ____, "Analog CMOS current-mode implementation of the feedforward neural network with on-chip learning and storage," in Proc. IEEE Int. Conf. Neural Networks, 1995, pp. 645-650.
17. C.-Y. Wu and C.-H. Cheng, "The design of CMOS modified Hopfield neural network for pattern recognition," in Proc. Int. Symp. Multimedia Information, 1997, pp. 585-590.
18. J. A. Freeman and D. M. Skapura, Neural Networks-Algorithms, Applications and Programming Techniques. Reading, MA: Addison-Wesley, 1992.
19. C.-Y. Wu and C.-H. Cheng, "The design of cellular neural network with ratio memory for pattern learning and recognition," in Proc. IEEE 6th Int. Workshop Cellular Neural Network and their Applications, 2000, pp. 301-307.
20. ____, "A new analog multiplier-divider with compact structure for CMOS neural network applications," in Proc. 1st Asia Pacific Conf. on ASICs, 1999, pp. 315-317.
21. C.-Y. Wu, C.-C. Hsieh, F.-W. Jih, T.-P. Sun, and S.-J. Yang, "A new share-buffered direct-injection readout structure for infrared detector," in Proc. SPIE Infrared Technology XIX, vol. 2020, 1993, pp. 57-64.