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Volumn 35, Issue 12, 2002, Pages 29-34
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Reducing SoC simulation and development time
a
a
Tensilica
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(United States)
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Author keywords
[No Author keywords available]
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Indexed keywords
REGISTER-TRANSFER-LEVEL HARDWARE;
SYSTEM-ON-CHIP;
ALGORITHMS;
COMPUTER HARDWARE;
EMBEDDED SYSTEMS;
INTEGRATED CIRCUIT LAYOUT;
LOGIC DESIGN;
LOGIC GATES;
MICROPROCESSOR CHIPS;
SOFTWARE ENGINEERING;
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EID: 0036937547
PISSN: 00189162
EISSN: None
Source Type: Trade Journal
DOI: 10.1109/MC.2002.1106176 Document Type: Article |
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Times cited : (20)
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References (0)
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