High performance copper and low-k interconnect technology fully compatible to 90 nm-node SOC application (CMOS4)

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 77-80

  Inohara, M ^a   Tamura, I ^a   Yamaguchi, T ^a   Koike, H ^a   Enomoto, Y ^b   Arakawa, S ^a   Watanabe, T ^a   Ide, E ^a   Kadomura, S ^b   Sunouchi, K ^a  

^a TOSHIBA CORPORATION   (Japan)

^b SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; COPPER; DYNAMIC RANDOM ACCESS STORAGE; ELECTRONICS PACKAGING; INTERCONNECTION NETWORKS; TRANSISTORS;

MEMORY REDUNDANCY;

CMOS INTEGRATED CIRCUITS;

EID: 0036932005     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. K.C.Yu, et al, IITC, 2002
2. M.Fayolle, et al, IITC, 2002
3. K.Miyashita, et al, VSLI Symp., p11, 2001
4. H.Yosiura, et al, VLSI Symp., p143, 2001
5. K.Higashi, et al, IITC, 2002
6. Anand T.Krishnan, et al, IEDM, p865, 2001
7. N.Matsunaga, et al, PPID, p142, 2002