Simulation based cause and effect analysis of cycle time and WIP in semiconductor wafer fabrication

Winter Simulation Conference Proceedings

Volumn 2, Issue , 2002, Pages 1423-1430

  Qi, Chao ^a   Tang, Tuck Keat ^b   Sivakumar, Appa Iyer ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER SOFTWARE; PROCESS ENGINEERING; PRODUCTION CONTROL; SCHEDULING; THROUGHPUT; WSI CIRCUITS;

WORK-IN-PROCESS (WIP);

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0036923659     PISSN: 02750708     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. Bai, X., and S.B. Gershwin, 1990, "A manufacturing Scheduler's Perspective on Semiconductor Fabrication," VLSI Memo No. 89-518, Massachusetts Institute of Technology.
2. Bonvik, A.M., 1996, "Performance Analysis of Manufacturing Systems Under Hybrid Control Policies," Dissertation for Ph.D. degree in MIT.
3. Feigin, G., J.W. Fowler, J. Robinson, and R. Leachman, 1994, "Semiconductor wafer manufacturing data format specification", Dataset of International SEMATECH.
4. Fowler, J.W., N. Phojanamongkolkij, J.K. Cochran, and D.C. Montgomery, 2002, "Optimal batching in a wafer fabrication facility using a multiproduct G/G/c model with batch processing," International Journal of Production Research, Vol. 40, No. 2, pp. 275-292.
5. Glassey, C.R., and M.G.C. Resende, 1988, "Closed-loop job release control for VLSI circuit manufacturing," IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 1, pp. 36-46.
6. Harrison, J.M., C.A. Holloway, and J.M. Patell, 1990, "Measuring Delivery Performance: A Case Study from the Semiconductor Industry," Measures for Manufacturing Excellence, R.S. Kaplan (ed.), Harvard Business School Press.
7. Hopp, W.J., and L. Spearman, 2000, Factory Physics: Foundations of Manufacturing Management, International Edition, Irwin/McGraw-Hill.
8. Hughes, R.A., and J.D. Shott, 1986, "The future of automatics for high-volume wafer fabrication and ASIC manufacturing," Proceedings of the IEEE, Vol. 74, No. 12, pp. 1775-1793.
9. Kiran, A.S., 1998, Simulation and Scheduling, In Handbook of Simulation, ed. J. Banks, pp. 677-717, New York: John Wiley & Sons.
10. Law, A.M., and W.D. Kelton, 1991, Simulation Modeling and Analysis, Second Edition, McGraw-Hill.
11. Levinstein, H.J., 1990, "White paper on IC fabrication in the coming 2000" Research Report T90150, Semiconductor Research Operation, Research Triangle Park, NC 27790.
12. Lin, C.Y., 1996, "Shop floor scheduling of semiconductor wafer fabrication using real-time feedback control and predictions," A dissertation for Ph.D. degree, University of California at Berkeley.
13. Mazziotti, B.W., and Jr.R.E. Home, 1997, "Creating a flexible, simulation-based finite scheduling tools," Proceeding of the 1997 Winter Simulation Conference, ed. S. Andradottir, K.J. Healy, D.H. Withers, and B.L. Nelson, 853-858. Institute of Electrical and Electronics Engineers, Piscataway, New Jersey.
14. Morito, S., and K.H. Lee, 1997, "Efficient simulation / optimization of dispatching priority with "fake" processing time," Proceedings of the 1997 Winter Simulation Conference, ed. S. Andradottir, K.J. Healy, D.H. Withers, and B.L. Nelson, pp. 872-879. Institute of Electrical and Electronics Engineers, Piscataway, New Jersey.
15. Sivakumar, A.I., 2000, "Simulation based cause and effect analysis of cycle time distribution in semiconductor backend," Proceedings of the 2000 Winter Simulation Conference.
16. Sivakumar, A.I., and C.S. Chong, 2001, "A simulation based analysis of cycle time distribution, and throughput in semiconductor backend manufacturing," Computers in Industry, Vol. 45, pp. 59-78.
17. Spearman, M. L., D.L. Woodruff, and W.J. Hopp, 1990, "CONWIP: A Pull Alternative to Kanban," International Journal of Production Research, Vol. 28, No. 5, pp. 879-894.
18. Uzsoy, R., C.Y. Lee, and L.A. Martin-vega, 1992, "A review of production planning and scheduling models in the semiconductor industry - Part I: System characteristics, performance evaluation and production planning," IIE Transactions, Vol. 24, No. 4, pp. 47-60.
19. Uzsoy, R., C.Y. Lee, and L.A. Martin-vega, 1994, "A review of production planning and scheduling models in the semiconductor industry - Part II: shop-floor control," IIE Transactions, Vol. 26, No. 5, 44-55.
20. Wein, L.M., 1988, "Scheduling semiconductor wafer fabrication," IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 3, pp. 115-130.