Reliability studies and design improvement of mirror image CSP assembly

Microelectronics Reliability

Volumn 42, Issue 12, 2002, Pages 1931-1937

  Xie, Dongji ^a   Yi, Sammy ^a  

^a FLEXTRONICS INTERNATIONAL   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSEMBLY; COMPUTER SIMULATION; ELECTRONIC EQUIPMENT TESTING; FINITE ELEMENT METHOD; IMAGE ANALYSIS; MATRIX ALGEBRA; MIRRORS; PRINTED CIRCUIT BOARDS; SOLDERED JOINTS; STRAIN; STRESS ANALYSIS; THERMAL CYCLING;

MIRROR IMAGES;

CHIP SCALE PACKAGES;

EID: 0036890937     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(02)00124-5     Document Type: Article

References (6)

1. http://www.toshiba.co.jp/about/press/1999_05/pr1001.htm.
2. Chaffarian R. Chip Scale Review. (November/December):1999.
3. Nakajima K., Lewis A., et al. Proc. IPC Chip Scale and BGA National Symposium, May 6-7, Part II. p. 52-58.
4. Solomon H.D. Fatigue of 60/40 Solder. IEEE Trans. CHMT. 9(4):1986;423-432.
5. Gintic Institute of Manufacturing Technology. Final Report of CSP Consortium II, 1999. Chapter 3.
6. IPC Standard, IPC-6012A, p. 8.