Fabrication of GaAs MISFET with nm-thin oxidized layer formed by UV and ozone process

IEEE Transactions on Electron Devices

Volumn 49, Issue 11, 2002, Pages 1856-1862

  Iiyama, Koichi ^a   Kita, Yukihiro ^a   Ohta, Yosuke ^a   Nasuno, Masaaki ^a   Takamiya, Saburo ^a   Higashimine, Koichi ^b   Ohtsuka, Nobuo ^b  

^a KANAZAWA UNIVERSITY   (Japan)

^b JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

Compound semiconductors; GaAs; MISFET; Self align; Ultraviolet (UV) and ozone process

Indexed keywords

LEAKAGE CURRENTS; NATURAL FREQUENCIES; OZONE; SEMICONDUCTING GALLIUM ARSENIDE; ULTRAVIOLET RADIATION;

CUTTOFF FREQUENCIES;

MISFET DEVICES;

EID: 0036867009     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.804720     Document Type: Article

References (14)

1. Y. Yamashita, A. Endoh, K. Shinohara, M. Higashiwaki, K. Hikosaka, T. Mimura, S. Hiyamizu, and T. Matsui, "Ultrashort 25-nm-gate lattice-matched InAlAs/InGaAs HEMTs within the range of 400 GHz cutoff frequency," IEEE Electron Device Lett., vol. 22, pp. 367-169, Aug. 2001.
2. L.D. Nguyen, A.S. Brown, M.A. Thompson, and L.M. Jelloian, "50-nm self-aligned-gate pseudomorphic AlInAs/GaInAs high-electron mobility transistors," IEEE Trans. Electron Devices, vol. 39, pp. 2007-20 014, Sept. 1992.
3. T. Sugimura, T. Tsuzuku, Y. Kasai, K. Iiyama, and S. Takamiya, "I-V characteristics of Schottky/metal-insulator-semiconductor diodes with tunnel thin barriers," Jpn. J. Appl. Phys., pt. I, vol. 39, no. 7B, pp. 4521-4522, 2000.
4. Y.G. Xie, S. Kasai, H. Takahashi, C. Jiang, and H. Hasegawa, "Low leakage, high breakdown voltage and high transconductance insulated gate PHEMTs utilizing silicon interface control layer," in Proc. TWHM, Kyoto, Japan, 2000, pp. 24-25.
5. 3) as gate oxide," Solid State Electron., vol. 41, p. 1751, 1997.
6. 2 films on gallium arsenide," Solid State Electron., vol. 44, pp. 1917-1923, 2000.
7. J.-Y. Wu, H.-H. Wang, Y.-H. Wang, and M.-P. Houng, "Fabrication of depletion-mode GaAs MOSFET with a selective oxidation process by using metal as the mask," IEEE Electron Device Lett., vol. 22, pp. 2-4, Jan. 2001.
8. T. Sugimura, T. Tsuzuku, T. Katsui, Y. Kasai, T. Inokuma, S. Hashimoto, K. Iiyama, and S. Takamiya, "A preliminary study of MIS diodes with nm-thin GaAs-oxide layers," Solid State Electron., vol. 43, no. 8, pp. 1571-1576, 1999.
9. Y. Kita, Y. Ohta, N.C. Paul, K. Iiyama, and S. Takamiya, "Depletion and accumulation mode operation of GaAs MISFET with nm-thin gate insulating layers formed by UV and ozone process," in Proc. 28th ISCS, vol. 56, Tokyo, Japan, 2001, p. 56.
10. M. Hiroshima, T. Yasaka, S. Miyazaki, and M. Hirose, "Electron tunneling through ultrashin gate oxide formed on hydrogen-terminated Si (100) surfaces," Jpn. J. Appl. Phys., vol. 33, no. 1B, pp. 395-398, 1994.
11. M. Fujimura, H. Nohira, and T. Hattori, "Surface morphology of ultrathin thermal oxide film formed on Si (100) surface," in Proc. 4th Workshop Formation Characterizaion Reliability of Ultrathin Silicon Oxide Films, 1999, JSAP Catalog No: AP992 204, pp. 275-279.
12. N.C. Paul, Y. Ohta, D. Tezuka, M. Nasuno, Y. Yamamura, T. Inokuma, K. Iiyama, and S. Takamiya, "Quality improvement of oxidized-GaAs/n -GaAs structure by nitrogen plasma treatment," in Proc. 14th Indium Phosphide and Related Materials Conf., Stockholm, Sweden, 2002, pp. 217-220.
13. N.C. Paul, D. Tezuka, T. Inokuma, K. Iiyama, and S. Takamiya, "Effect of oxidation and/or nitridation of (100) n -GaAs surface," in Abstract Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Sapporo, Japan, 2002, pp. 253-256.
14. M. Passlack, M. Hong, E.F. Schubert, G.J. Zydzik, J.P. Mannaerts, W.S. Hobson, and T.D. Harris, "Advancing metal-oxide-semiconductor theory: Steady-state nonequilibrium conditions," J. Appl. Phys., vol. 81, no. 11, pp. 7647-7661, 1997.