The digital front-end electronics for the space-borne INTEGRAL-SPI experiment: ASIC design, design for test strategies and self-test facilities

IEEE Transactions on Nuclear Science

Volumn 49 II, Issue 5, 2002, Pages 2492-2496

  Mur, Michel ^a   Cordier, B ^a   Donati, M ^a   Duc, R ^a   Fallou, J L ^a   Larque T ^a   Louis, F ^a   Schanne, S ^a   Zonca, E ^a  

^a CEA SACLAY   (France)

Author keywords

Application specific integrated circuit (ASIC) design; Built in self test; Design for test

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT LAYOUT; SATELLITES; TEST FACILITIES;

DIGITAL FRONT END ELECTRONICS; SATELLITE SPACECRAFT; VERY HIGH SPEED INTEGRATED CIRCUIT DESCRIPTION LANGUAGE;

GAMMA RAY SPECTROMETERS;

EID: 0036816538     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2002.803855     Document Type: Article

References (3)

1. C. Winkler, "INTEGRAL: Overview and mission concept," Astrophys. J., June 1994.
2. S. Schanne, B. Cordier, M. Gros, M. Mur, S. Crespin, and S. Joly, "The space-borne INTEGRAL-SPI gamma ray telescope: Test and calibration campaigns," IEEE Trans. Nucl. Sci., to be published.
3. E. Lafond, M. Mur, and S. Schanne, "The digital ASIC for the digital front end electronics of the SPI astrophysics gamma-ray experiment," IEEE Trans. Nucl. Sci., vol. 45, pp. 1836-1839, Aug. 1998.