SCOPUS 정보 검색 플랫폼

IEEE Transactions on Applied Superconductivity

Volumn 12, Issue 3, 2002, Pages 1872-1875

A hybrid Nb/CMOS integration process for superconducting tunnel junction imaging arrays

(3) Wong, Andre b,c Meng, Xiaofan b Van Duzer, Theodore a,b

a IEEE (United States)

b UNIVERSITY OF CALIFORNIA (United States)

c JDS UNIPHASE (United States)

Author keywords

Hybrid structures; Nb AlO x Nb; Planarization; Superconducting tunnel junctions

Indexed keywords

IMAGING ARRAYS;

CHEMICAL MECHANICAL POLISHING; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRON CYCLOTRON RESONANCE; IMAGING SYSTEMS; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SILICON WAFERS; TUNNEL JUNCTIONS;

SEMICONDUCTOR JUNCTIONS;

EID: 0036732063 PISSN: 10518223 EISSN: None Source Type: Journal
DOI: 10.1109/TASC.2002.802945 Document Type: Article

Times cited : (1)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.