A constructive genetic algorithm for gate matrix layout problems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 8, 2002, Pages 969-974

  De Oliveira, Alexandre C M ^a   Lorena, Luiz A N ^b  

^a FEDERAL UNIVERSITY OF MARANHÃO   (Brazil)

^b INSTITUTO NACIONAL DE PESQUISAS ESPACIAIS   (Brazil)

Author keywords

Constructive genetic algorithms; Gate matrix layout; VLSI layout design

Indexed keywords

GENETIC ALGORITHMS; HEURISTIC METHODS; LOGIC GATES; MATHEMATICAL OPERATORS; MATRIX ALGEBRA; VLSI CIRCUITS;

GATE MATRIX LAYOUT PROBLEMS (GMLP);

INTEGRATED CIRCUIT LAYOUT;

EID: 0036683915     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.800454     Document Type: Article

References (13)

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