Integrated performance models for SPMD applications and MIMD architecture

IEEE Transactions on Parallel and Distributed Systems

Volumn 13, Issue 7, 2002, Pages 745-757

  Cremonesi, Paolo ^a   Gennaro, Claudio ^b  

^a POLITECNICO DI MILANO   (Italy)

^b ISTI CNR   (Italy)

Author keywords

Fork join queues; Mean value analysis (MVA); Multiple instruction multiple data (MIMD); Parallel I O; Performance model; Queuing network model; Single program multiple data (SPMD); Speedup surface; Synchronization overhead

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; TOPOLOGY;

MULTIPLE INSTRUCTION MULTIPLE DATA (MIMD) ARCHITECTURES; SINGLE PROGRAM MULTIPLE DATA (SPMD) ARCHITECTURES;

QUEUEING NETWORKS;

EID: 0036649292     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2002.1019862     Document Type: Article

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