New fabrication technique for nano-MOS transistors with W=25 nm and L=25 nm using only conventional optical lithography

Microelectronic Engineering

Volumn 61-62, Issue , 2002, Pages 601-605

  Horstmann, John T ^a   Goser, K F ^a  

^a TU DORTMUND UNIVERSITY   (Germany)

Author keywords

CMOS process; Lithography; MOS transistor; Nanostructure; Sub 100 nm dimensions

Indexed keywords

CMOS INTEGRATED CIRCUITS; NANOSTRUCTURED MATERIALS; PHOTOLITHOGRAPHY; TRANSISTORS;

MASK LAYERS;

MOS DEVICES;

EID: 0036643576     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(02)00430-6     Document Type: Conference Paper

References (4)

1. Noise analysis of sub-100-nm MOS transistors fabricated by a special deposition and etchback technique
2. 1/f Noise of sub-100-nm MOS transistors fabricated by a special deposition and etchback technique
3. Matching analysis of deposition defined 50 nm MOSFETs