Calibration of parallel ΔΣ ADCs

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 49, Issue 6, 2002, Pages 390-399

  Batten, Robert D ^a   Eshraghi, Aria ^b,c   Fiez, Terri S ^a  

^a Oregon State University   (United States)

^b IBM   (United States)

^c SILICON LABORATORIES   (United States)

Author keywords

ADC; modulation; Analog to digital converter (ADC); Calibration; Oversampling modulator; Parallel architecture; Resolution

Indexed keywords

ALGORITHMS; BANDWIDTH; CALIBRATION; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; MODULATORS;

HADAMARD MATRIX; PARALLEL ARCHITECTURE;

ANALOG TO DIGITAL CONVERSION;

EID: 0036624687     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2002.803468     Document Type: Article

References (16)

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