ASIC wafer test system for the ATLAS semiconductor tracker front-end chip

IEEE Transactions on Nuclear Science

Volumn 49 II, Issue 3, 2002, Pages 1080-1085

  Anghinolfi, F ^a   Bialas, W ^b   Busek, N ^c   Ciocio, A ^c   Cosgrove, D ^d   Fadeyev, V ^c   Flacco, C ^d   Gilchriese, M ^c   Grillo, A A ^d   Haber, C ^c   Kaplon, J ^a   Lacasta, C ^e   Murray, W ^f   Niggli, H ^c   Pritchard, T ^g   Rosenbaum, F ^d   Spieler, H ^c   Stezelberger, T ^c   Vu, C ^c   Wilder, M ^d   Yaver, H ^c   Zetti, F ^c   more..

^a CERN   (Switzerland)

^b AGH UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Poland)

^c LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

^d UNIVERSITY OF CALIFORNIA SANTA CRUZ   (United States)

^e INSTITUTO DE FÍSICA CORPUSCULAR IFIC   (Spain)

^f RUTHERFORD APPLETON LABORATORY   (United Kingdom)

^g QUEEN MARY UNIVERSITY OF LONDON   (United Kingdom)

Author keywords

Field programmable gate arrays (FPGAs); Integrated circuit testing; LHC experiments; Measurement system data handling; Particle tracking; Silicon radiation detectors

Indexed keywords

EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS; GAIN MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; PARTICLE DETECTORS; SILICON WAFERS; SPURIOUS SIGNAL NOISE;

APPLICATION-SPECIFIC INTEGRATED CIRCUITS; ELECTRONIC NOISE; PROBE CARD; SEMICONDUCTOR TRACKER; TIME RESOLUTION;

PARTICLE BEAM TRACKING;

EID: 0036624455     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2002.1039618     Document Type: Article

References (9)

1. W. Dabrowski. (2001, June) ABCD3TA ASIC requirements and specifications. ATLAS Project Document ATL-IS-ES-0039. [Online]. Available: http://scipp.ucsc.edu/groups/atlas/prr-doc/ABCD3TA_spec_v1.3.pdf
2. T. Dubbs et al., "The development of the CAFE-P/CAFE-M bipolar chips for the ATLAS semiconductor tracker," in Proc. 5th Workshop Electronics for LHC Experiments, Snowmass, CO, 1999, pp. 123-127.
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6. I. G. Volobouev, private communication, Lawrence Berkeley National Laboratory, Berkeley, CA, 2000.
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9. C. Flacco, A. Ciocio, and V. Fadeyev, "Optimization of repetition parameters for ABCD3T chip analog tests," ATLAS Collaboration internal note ATL-INDET-2002-008.