Power distribution analysis of VLSI interconnects using model order reduction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 6, 2002, Pages 739-745

  Shin, Youngsoo ^a   Sakurai, Takayasu ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

Interconnect; Model order reduction; VLSI

Indexed keywords

CAPACITANCE; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER DISTRIBUTION; TRANSFER FUNCTIONS;

VLSI INTERCONNECTS;

VLSI CIRCUITS;

EID: 0036609576     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.1004318     Document Type: Article

References (8)

1. Interconnect scaling - The real limiter to high performance ULSI
2. Asymptotic waveform evaluation for timing analysis
3. PRIMO: Probability interpretation of moments for delay calculation
4. Approximation of wiring delay in MOSFET LSI
5. Efficient linear circuit analysis by Padé approximation via the Lanczos process