Some fundamentals of wafer-level packaging

Solid State Technology

Volumn 45, Issue 6, 2002, Pages 105-113

  Patterson, Deborah S ^a  

^a Flip Chip Division   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE; DIELECTRIC MATERIALS; DYNAMIC RANDOM ACCESS STORAGE; EUTECTICS; SILICON WAFERS; SOLDERED JOINTS; STATIC RANDOM ACCESS STORAGE; SURFACE MOUNT TECHNOLOGY; THERMAL CYCLING; THIN FILMS;

WAFER-LEVEL PACKAGING (WLP);

CHIP SCALE PACKAGES;

EID: 0036603243     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (2)

1. Deformation and crack growth characteristics of SnAgCu vs. 63 Sn/Pb solder joints on a WLP in thermal cycle testing