Time-minimal tiling when rise is larger than zero

Parallel Computing

Volumn 28, Issue 6, 2002, Pages 915-939

  Xue, Jingling ^a   Cai, Wentong ^b  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Loop nest; Loop tiling; Optimising compiler; SPMD

Indexed keywords

CODES (SYMBOLS); COSTS; DATA STORAGE EQUIPMENT; ITERATIVE METHODS; OPTIMIZATION; THEOREM PROVING;

LOOP TILING;

DISTRIBUTED COMPUTER SYSTEMS;

EID: 0036601528     PISSN: 01678191     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-8191(02)00098-4     Document Type: Article

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