메뉴 건너뛰기




Volumn 32, Issue 3, 2002, Pages 428-436

A knowledge-based expert system for automatic visual VLSI reverse-engineering: VLSI layout version

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; KNOWLEDGE REPRESENTATION; LOGIC DESIGN; MICROPROCESSOR CHIPS; REVERSE ENGINEERING; VLSI CIRCUITS;

EID: 0036589528     PISSN: 10834427     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSMCA.2002.805765     Document Type: Letter
Times cited : (10)

References (18)
  • 1
    • 0025559145 scopus 로고
    • AI techniques and object-oriented technology for VLSI design space representation, optimization, and management
    • Bellingham, WA: SPIE
    • A. Hekmatpour and P. Chau, "AI techniques and object-oriented technology for VLSI design space representation, optimization, and management," in Applications of Artificial Intelligence VIII. Bellingham, WA: SPIE, 1990, vol. 1293, pp. 85-94.
    • (1990) Applications of Artificial Intelligence VIII , vol.1293 , pp. 85-94
    • Hekmatpour, A.1    Chau, P.2
  • 2
    • 0024876417 scopus 로고    scopus 로고
    • An environment for the development of KBd expert systems for assistance to VLSI design
    • R. F. Jacome and M. A. Lanca, "An environment for the development of KBd expert systems for assistance to VLSI design," in Proc. Mediterranean Electrotechn. Conf., 1989, pp. 315-319.
    • Proc. Mediterranean Electrotechn. Conf., 1989 , pp. 315-319
    • Jacome, R.F.1    Lanca, M.A.2
  • 4
    • 0025405328 scopus 로고
    • A knowledge-based framework of VLSI design
    • Mar.
    • M. Loupis and G. Tziallas, "A knowledge-based framework of VLSI design," J. Microprocess. Microprogram., vol. 28, no. 1-5, pp. 327-331, Mar. 1990.
    • (1990) J. Microprocess. Microprogram. , vol.28 , Issue.1-5 , pp. 327-331
    • Loupis, M.1    Tziallas, G.2
  • 5
    • 0024866182 scopus 로고    scopus 로고
    • From expert assistant to design verification applications of AI to VLSI design
    • A. Miller, "From expert assistant to design verification applications of AI to VLSI design," in Proc. IEEE Southeastcon, 1989, pp. 406-409.
    • Proc. IEEE Southeastcon, 1989 , pp. 406-409
    • Miller, A.1
  • 6
    • 0026051095 scopus 로고
    • Expert compactor: A knowledge-base application in VLSI layhout compaction
    • Jan.
    • P. Y. Hsiao and C. C. Tsai, "Expert compactor: A knowledge-base application in VLSI layhout compaction," Proc. IEEE, vol. 138, pp. 13-20, Jan. 1991.
    • (1991) Proc. IEEE , vol.138 , pp. 13-20
    • Hsiao, P.Y.1    Tsai, C.C.2
  • 7
    • 0024715683 scopus 로고
    • Partitioning of digital designs: Knowledge based approach and concepts for its parallelization
    • Aug.
    • M. Hulin and J. Heistermann, "Partitioning of digital designs: Knowledge based approach and concepts for its parallelization," J. Microprocess. Microprogram., vol. 27, no. 1-5, pp. 69-75, Aug. 1989.
    • (1989) J. Microprocess. Microprogram. , vol.27 , Issue.1-5 , pp. 69-75
    • Hulin, M.1    Heistermann, J.2
  • 10
    • 0011980982 scopus 로고
    • Specifications for the development of a knowledge-based image-interpretation system
    • June
    • T. R. Gowrishankar and N. G. Bourbakis, "Specifications for the development of a knowledge-based image-interpretation system," Int. J. Eng. Applicat. AI, vol. 3, June 1990.
    • (1990) Int. J. Eng. Applicat. AI , vol.3
    • Gowrishankar, T.R.1    Bourbakis, N.G.2
  • 12
    • 85013586420 scopus 로고    scopus 로고
    • Specifications for the development of an expert tool for the automatic optical understanding of electronic circuits: VLSI reverse engineering
    • N. G. Bourbakis, and C. V. Ramamoorthy, "Specifications for the development of an expert tool for the automatic optical understanding of electronic circuits: VLSI reverse engineering," in Proc. IEEE VLSI Test Symp., 1991, pp. 98-103.
    • Proc. IEEE VLSI Test Symp., 1991 , pp. 98-103
    • Bourbakis, N.G.1    Ramamoorthy, C.V.2
  • 13
    • 0024301358 scopus 로고
    • Geometric transformations of optimum VLSI layout placement
    • N. Bourbakis and I. N. Savvides, "Geometric transformations of optimum VLSI layout placement," J. Microprocess. Microprogram., vol. 25, pp. 163-170, 1989.
    • (1989) J. Microprocess. Microprogram. , vol.25 , pp. 163-170
    • Bourbakis, N.1    Savvides, I.N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.