Automatic partitioning of parallel loops with parallelepiped-shaped tiles

IEEE Transactions on Parallel and Distributed Systems

Volumn 13, Issue 5, 2002, Pages 460-470

  Rastello, Fabrice ^b   Robert, Yves ^a,c,d  

^a IEEE   (France)

^b STMICROELECTRONICS   (France)

^c CNRS   (France)

^d UNIVERSITÉ DE LYON   (France)

Author keywords

Cache; Compilation technique; Data locality; Footprint; Hierarchical memory systems; Loop partitioning; Out of corealgorithms; Tiling

Indexed keywords

LOOP PARTITIONING;

ALGORITHMS; APPROXIMATION THEORY; CACHE MEMORY; DATA REDUCTION; DATA STORAGE EQUIPMENT; HIERARCHICAL SYSTEMS; OPTIMIZATION;

PARALLEL PROCESSING SYSTEMS;

EID: 0036565622     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2002.1003856     Document Type: Article

References (15)

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