Evaluation of CVD/PVD multilayered seed for electrochemical deposition of Cu-damascene interconnects

IEEE Transactions on Electron Devices

Volumn 49, Issue 5, 2002, Pages 733-738

  Furuya, Akira ^a   Tagami, Masayoshi ^a   Shiba, Kazutoshi ^a   Kikuta, Kuniko ^a   Hayashi, Yoshihiro ^a  

^a NEC CORPORATION   (Japan)

Author keywords

Copper; CVD; ECD; Interconnects; PVD; Seed

Indexed keywords

CHEMICAL MECHANICAL POLISHING; CHEMICAL VAPOR DEPOSITION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC RESISTANCE; ELECTROMIGRATION; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; OSCILLATORS (ELECTRONIC); PHYSICAL VAPOR DEPOSITION; SEMICONDUCTING FILMS; ULSI CIRCUITS;

DAMASCENE INTERCONNECTS; ELECTROCHEMICAL DEPOSITION; MULTILAYERED SEED; PROPAGATION DELAY; RING-OSCILLATOR CIRCUITS;

COPPER;

EID: 0036564014     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.998578     Document Type: Article

References (5)

1. An inlaid CVD Cu based integration for sub 0.25 μm technology
2. CVD Cu seed layer development for via and trench fill with PVD Cu and electroplating
3. Effect of texture and grain structure on electromigration in Al-0.5% Cu thin films
4. Effect of texture on the electromigration of CVD copper
5. 2 CMOS SRAM technology using self-aligned local interconnect and copper interconnect metallization