VLSI architecture for SAR data compression

IEEE Transactions on Aerospace and Electronic Systems

Volumn 38, Issue 2, 2002, Pages 427-440

  Jeong, H ^a,c   Park, J H ^b   Ryu, H Y ^c   Kwon, J B ^b   Oh, Y ^c  

^a IEEE   (South Korea)

^b LG Innoteck Corporation   (South Korea)

^c Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; CORRELATORS; DATA COMPRESSION; FIELD PROGRAMMABLE GATE ARRAYS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

SIGNAL APERTURE RADAR (SAR) CORRELATORS;

RADAR SYSTEMS;

EID: 0036544412     PISSN: 00189251     EISSN: None     Source Type: Journal    
DOI: 10.1109/TAES.2002.1008977     Document Type: Article

References (19)

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13. Image formation from spaceborne synthetic aperture radar signals
14. A SAR correlation algorithm which accomondates large-range migration