A new structure for in-depth history effect characterization on partially depleted SOI transistors

IEEE International SOI Conference

Volumn , Issue , 2002, Pages 35-36

  Faynot, O ^a   Poiroux, T ^a   Cluzel, J ^a   Belleville, M ^a   De Pontcharra, J ^a  

^a CEA GRENOBLE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC INVERTERS; INTEGRATED CIRCUIT LAYOUT; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS;

HISTORY EFFECTS;

TRANSISTORS;

EID: 0036458610     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2002.1044405     Document Type: Conference Paper

References (3)

1. F. Assaderaghi et al., Proc. Symp. On VLSI Technologies, p.122, 1996.
2. M. Pellela et al., IEDM'99, p.831, 1999.
3. O. Faynot et al., Solid State Electronics, p.599, 2001.