Design optimization of One-Turn Helix - A novel compliant off-chip interconnect

Thermomechanical Phenomena in Electronic Systems -Proceedings of the Intersociety Conference

Volumn , Issue , 2002, Pages 833-839

  Zhu, Qi ^a   Ma, Lunyu ^a   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Compliance; CTE; Design; Inductance; Interconnect; Optimization; Resistance; Respon se; Wafer level

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; OPTIMIZATION; PARAMETER ESTIMATION; SILICON WAFERS; THERMAL EXPANSION;

OFF-CHIP INTERCONNECTS;

CHIP SCALE PACKAGES;

EID: 0036457588     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. http://public.itrs.net, International Technology Roadmap for Semiconductors, 2000 update.
2. Zhu, Q., Ma, L., and Sitaraman, S.K., "Mechanical and Preliminary Electrical Design of a Novel Compliant One - Turn Helix (OTH) Interconnect," Proceedings of IPACK'01, 2001.
3. Brown, W.D., Advanced Electronic Packaging, IEEE Press, New York (1999), pp95-96.
4. Grover, F.W., Inductance Calculations Working Formulas and Tables, D. Van Nostrand, New York (1980), pp164-166.
5. Tummala, R.R., Fundamentals of Microsystems Packaging, Mc-Graw-Hill, (2001):, pp124.
6. Myers, R.H. and Montgomery, D.C., Response Surface Methodology: Process and Product Optimization Using Designed Experiments, John Wiley & Sons, New York (1995).
7. Internal Report on Mechanical and Electrical Considerations of Compliant Interconnect, Intel Corporation, 2001.