An ESD protection circuit for SOI technology using gate- and body-biased MOSFET's

IEEE International SOI Conference

Volumn , Issue , 2002, Pages 45-46

  Salman, Akram ^a   Mitra, Souvick ^a   Ioannou, Dimitris E ^a   Fechner, Paul ^b   Liu, Mike ^b  

^a GEORGE MASON UNIVERSITY   (United States)

^b HONEYWELL TECHNOLOGY CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC INVERTERS; INTEGRATED CIRCUIT LAYOUT; IRRADIATION; LEAKAGE CURRENTS; SILICON ON INSULATOR TECHNOLOGY; X RAYS;

PROTECTION CIRCUITS;

MOSFET DEVICES;

EID: 0036454663     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2002.1044410     Document Type: Conference Paper

References (4)

1. M. Chan et al., 1994 IRPS Proc., p. 292.
2. J.P. Colinge, "SOI Technology", Kluwer, 1997.
3. S. Voldmann et al., 1997 EOS/ESD Symp., p210.
4. C. Duvvurry et al., 1996 VLSI Tech. Dig., p194.