Reliable worst-case tolerance design of feedback regulated DC-DC converters by evolutionary algorithms and interval arithmetic

PESC Record - IEEE Annual Power Electronics Specialists Conference

Volumn 4, Issue , 2002, Pages 1728-1736

  Femia, N ^a   Spagnuolo, G ^a  

^a UNIVERSITY OF SALERNO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; FEEDBACK; FITS AND TOLERANCES; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; RELIABILITY; THRESHOLD VOLTAGE;

DESIGN CONSTRAINTS; INTERVAL ARITHMETIC; RELIABLE WORST CASE TOLERANCE DESIGN; TOLERANCE DESIGN;

ELECTRIC CONVERTERS;

EID: 0036442873     PISSN: 02759306     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. R.Spence, R.S.Soin: Tolerance design of electronic circuits, Addison Wesley Publishing Company, 1988.
2. G.Spagnuolo: "An interval arithmetic-based yield evaluation in circuit tolerance design", accepted for IEEE ISCAS 2002, Phoenix, U.S.A., June 2002.
3. J.Wojciechowski, J.Vlach: "Ellipsoidal method for design centering and yield estimation", IEEE Trans. On CAD, Vol.12, No. 10, Oct. 1993, pp. 1570-1579.
4. Michalewicks, Z.: Genetic Algorithms + Data Structures = Evolution Programs, Artificial Intelligence, Springer-Verlag, 1992.
5. R.E.Moore, Interval Analysis, Prentice Hall, Englewood Cliffs, NJ, 1996.
6. L.Jaulin et al.: Applied Interval Analysis, Springer, 2001.
7. R. W. Erickson, D. Maksimovic: Fundamentals of Power Electronics, 2nd ed., Dordrecht, The Netherlands, Kluwer, 2001.
8. M. Di Lorenzo del Casale, N.Femia, P.Lamberti, V.Mainardi, G.Spagnuolo, M.Vitelli: "Nominal and tolerance design of closet-loop controllers for dc-dc voltage regulators", accepted at IEEE ISCAS 2002, Phoenix, U.S.A., June 2002.