Gold stud bump in flip-chip applications

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2002, Pages 110-114

  Jordan, Jerry ^a  

^a Palomar Technologies Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; FLIP CHIP DEVICES; SOLDERING; SOLDERING ALLOYS;

GOLD BUMP PROCESS; GOLD STUD BUMP; WIRE BONDING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036398189     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Puttlitz, Karl J., "Area Array Technology: The Basics and Packaging/Assembly Innovations," Die and Packaging-Level Microelectronics Assembly: Base and Advanced Technology Course, San Diego, CA, Nov 2001.
2. Riley, George, "Bump, Dip, Flip: Single Chip," George Riley, Proceedings 1997 Surface Mount International, September 1987, pp. 535-541.
3. Lee, T. et al., "Gold Stud Bump Bonding for High Frequency Packaging: Impact of Gang Coining and other Process Variables on Electrical Properties," IMAPS Garden State Spring Packaging Symposium, May 2002.
4. Greig, W.J., Bendat, S., and Saba, V.R., "Flip Chip Technology-Achieving Precise Placement and Attachment," May 2002, p. 4.
5. "Comparison of Materials-Section A," Materials Engineering, Materials Selector, (Dec 1986), p. 28.