Encapsulation of 1-up fpBGA from design to production

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2002, Pages 183-189

  Sze, Henry M W ^a   Tsang, Raymond ^a   Jaramillo, Yerick ^a   Kuah, Eric ^a   Ho, S C ^a   Pang, David ^a   Weng, Ong Lee ^a  

^a 14/F QPL Industrial Building   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ENGINEERING; ELECTRONICS INDUSTRY; ENCAPSULATION; INTEGRATED CIRCUIT TESTING; MARKETING; MICROSCOPIC EXAMINATION; PRODUCT DESIGN; SURFACE MOUNT TECHNOLOGY;

PLASTIC NEAR CHIP SCALE BALL GRID ARRAY; SCANNING ACOUSTIC MICROSCOPY;

ELECTRONICS PACKAGING;

EID: 0036395477     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Kuah E., Ong L.W., "Molding Process of the 1Up-fpBGA Package", ASM Internal Report, MPET-00-012.
2. Kuah E., Ong L.W., "Molding Process Optimization of the 1Up-fpBGA Package Stage II", ASM Internal Report, MPET-00-013.
3. Kuah E., Ong L. W., Ng W., "Confirmation Run of 1Up-fpBGA Package Stage II", ASM Internal Report, MPET-00-014.
4. Mcllellan, N., Papageorge, M., Fan, N., "CSP Reliability: Meeting the Challenges", Advanced Packaging, February 1998.
5. Sze M. W., Papagoerge, M. "Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpBGA)", 4th Annual Flip Chip, BGA, Chip Scale Packaging Conference, April 28-29 1998.
6. Sze, M.W. "Competative Benchmarking Study for fpBGA", ASAT Internal Document TRMS-OTFP00-0103