A test processor concept for systems-on-a-chip

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 210-212

  Galke, C ^a   Pflanz, M ^a   Vierhaus, H T ^a  

^a BRANDENBURG UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; REDUCED INSTRUCTION SET COMPUTING; SHIFT REGISTERS; SIGNAL FILTERING AND PREDICTION;

DE-COMPACTION; EMBEDDED PROCESSORS; LINEAR FEEDBACK SHIFT REGISTER; SYSTEMS-ON-A-CHIP;

DESIGN FOR TESTABILITY;

EID: 0036395308     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Y Zorian, "Testing the Moster Chip", IEEE Spectrum Vol. 36 (7), July 1999, pp. 54-60
2. Y-. Zorian, E. J. Marinissen, S-. Dey, "Testing Embedded Core-Based System Chips", Proc. IEEE ITC, Oct. 1998, pp. 191-199
3. Y. Zorian, "Test Requirements for Embedded Core-Based systems and IEEE P 1500", Proc. IEEE ITC, Nov 1997, pp. 565-570
4. A. Irion, G. Kiefer, H. Vranken, H.-J. Wunderlich, "Circuit Partitioning for Efficient Logic BIST Synthesis", Proc. IEEE DATE, Mar. 2001, pp. 86-91
5. R. Dorsch, H. J. Wunderlich, "Reusing Scan Chains for Test Pattern Decompression", Proc. IEEE ETW, May 2001, pp. 124-132
6. R. Dorsch, H. J. Wunderlich, "Tailoring ATPG for Embedded Testing", Proc. IEEE ITC, Oct. 2001, pp. 530-537
7. S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois: "Built-in Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Register", IEEE Transactions on Computers, Vol. 44, No. 2, Febr. 1995, pp. 223-233
8. Koemann, B. "LFSR-Coded Test patterns for Scan Design", Proc. IEEE ITC, 1991, pp. 237-242
9. S. Hellebrand, H. J. Wunderlich, A. Hertwig: "Mixed Mode BIST Using Embedded Processors", Proc. IEEE ITC, Oct. 1996, pp. 195-204
10. M. Pflanz, F. Pompsch, H.T. Vierhaus: "An Efficient On-Line-Test and Back-up Scheme for Embedded Processors", Proc. IEEE ITC, Sep. 1999, pp. 964-972
11. J. Hennessy, D. Patterson: "Computer Architecture. A Quantitative Approach", Morgan Kaufmann Publishers, 1990
12. B. Koenemann, J. Mucha, G. Zwiehoff: "Built-in Logic Block Observation Techniques", Proc. IEEE ITC, 1979, pp. 37-41