Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2002, Pages

  U, Seng Pan ^a   Martins, R P ^a   Franca, J E ^a  

^a UNIVERSITY OF MACAU   (Macao)

Author keywords

[No Author keywords available]

Indexed keywords

DATA COMMUNICATION SYSTEMS; ELECTRIC CLOCKS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; SIGNAL TO NOISE RATIO; SWITCHED FILTERS; TIME VARYING SYSTEMS;

HIGH FREQUENCY FILTER; LOW TIMING-SKEW CLOCK; SWITCHED CAPACITOR FILTER; TIME INTERLEAVED SAMPLED DATA SYSTEMS;

TIMING CIRCUITS;

EID: 0036298625     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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7. Error analysis for time-interleaved analog channels
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9. Direct digital synthesizer with jittered clock
10. A 2.5V, 57MHz, 15-tap SC bandpass interpolating filter with 320MHz output sampling rate in 0.35μm CMOS