A genetic approach to analog module placement with simulated annealing

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages

  Zhang, Lihong ^a   Kleine, Ulrich ^a  

^a OTTO VON GUERICKE UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; GENETIC ALGORITHMS; HEURISTIC METHODS; LINEAR INTEGRATED CIRCUITS; MOS DEVICES; PARAMETER ESTIMATION; SIMULATED ANNEALING; TREES (MATHEMATICS);

ANALOG INTEGRATED CIRCUITS; ANALOG MODULE PLACEMENT; BINARY TREE; BOTTOM LEFT RELATIVE PLACEMENT; COST FUNCTION; SOFTWARE PACKAGE ALADIN; STEINER TREE PROBLEM;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036296552     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. The Timberwolf placement and routing package
2. A novel design tool for analog integrated circuits
3. KOAN/ANAGRAM II: New tools for device-level analog placement and routing
4. ILAC: An automated layout tool for analog CMOS circuits
5. A genetic approach to standard cell placement using meta-genetic parameter optimization
6. Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome
7. A genetic algorithm for macrocell placement
8. SAGA: A unification of the genetic algorithm with simulated annealing and its application to macro-cell placement
9. A novel design assistant for analog circuits
10. VLSI physical design automation (theory and practice)
11. An introduction to probability theory and mathematical statistics
12. Very fast simulated re-annealing