Noise analysis of power/ground planes on PCB by spice-like simulator with model order reduction technique

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Kubota, Hidemasa ^a   Kamo, Atsushi ^a   Watanabe, Takayuki ^a   Asai, Hideki ^a  

^a SHIZUOKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE;

CIRCUIT SIMULATORS; NOISE ANALYSIS; VOLTAGE CONTROLLED CURRENT SOURCE MODEL;

PRINTED CIRCUIT BOARDS;

EID: 0036296212     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Trend of circuit simulation based on electromagnetic field analysis and model order reduction techniques
2. Equivalent circuit models for three-dimensional multiconductor system
3. Modeling and analysis of multichip module power supply planes
4. Asymptotic waveform evaluation for timing analysis
5. Efficient linear circuit analysis by Padé approximation via the Lanczos process
6. PRIMA: Passive reduced-order interconnect macromodeling algorithm
7. Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations
8. SPADE: Analog/digital mixed signal simulator with analog hardware description language
9. ASSIST-α: An application of analog behavioral description by C/C++ language to ASSIST
10. Transient analysis for transmission line networks using expanded GMC
11. Synthesis of time-domain models for interconnects having 3-D structure based on FDTD method
12. A synthesis technique of time-domain interconnect models by MIMO type of selective orthogonal least square method