Power estimation at architecture level for embedded systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2002, Pages

  Mizuno, Hiroshi ^a   Kobayashi, Hiroyuki ^a   Onoye, Takao ^a   Shirakawa, Isao ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; ESTIMATION; RANDOM ACCESS STORAGE; ROM;

DIRECT MEMORY ACCESS; POWER ESTIMATION;

EMBEDDED SYSTEMS;

EID: 0036294607     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Efficient software performance estimation methods for hardware/software codesign
2. A statechart based HW/SW codesign system
3. Power estimation for architectural exploration of HW/SW communication on system-level buses
4. A framework for estimating and minimizing energy dissipation of embedded HW/SW systems
5. A low power hardware/software partitioning approach for core-based embedded systems
6. Cycle-accurate simulation of energy consumption in embedded systems
7. An instruction-level functionality-based energy estimation model for 32-bits microprocessors
8. Memory exploration for low power embedded systems