Improved cotransformation for LNS subtraction

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2002, Pages

  Arnold, Mark G ^a  

^a UNIVERSITY OF WYOMING   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGARITHMIC AMPLIFIERS; MATHEMATICAL MODELS; MATHEMATICAL TRANSFORMATIONS; MULTIPLYING CIRCUITS; NUMBER THEORY;

ARNOLD COTRANSFORMATION; ARNOLD LOGARITHMIC SUBTRACTION; COLEMAN LOGARITHMIC SUBTRACTION; LOGARITHMIC INTERPOLATOR; LOGARITHMIC NUMBER SYSTEMS;

DIGITAL ARITHMETIC;

EID: 0036292416     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. Redundant logarithmic arithmetic
2. Arithmetic co-transformations in the real and complex logarithmic number systems
3. Arithmetic co-transformations in the real and complex logarithmic number systems
4. A pipelined LNS ALU
5. Analysis of complex LNS FFTs
6. Simplification of table structure in logarithmic arithmetic
7. Digital filtering using logarithmetic arithmetic
8. Algorithm design for a 30-bit integrated logarithmic processor
9. An architecture for addition and subtraction of long world length numbers in the logarithmic number system
10. Interleaved memory function interpolators with application to an accurate LNS arithmetic unit
11. 114 MFLOPS logarithmic number system arithmetic unit for DSP applications
12. Novel algorithm for accurate logarithmic number system subtraction
13. Low power properties of the logarithmic number system
14. Logarithmic number system theory, analysis, and design
15. The sign/logarithm number system
16. Sign/logarithm arithmetic for FFT implementation
17. A 20 bit logarithmic number system processor