A low-noise nonlinear feedback technique for compensating offset in analog multipliers

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages

  Dastjerdi, Maziar Tavakoli ^a   Sarpeshkar, Rahul ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATTENUATION; BIPOLAR INTEGRATED CIRCUITS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; DEMODULATION; ELECTRIC NETWORK TOPOLOGY; FREQUENCY RESPONSE; LINEAR INTEGRATED CIRCUITS; MICROELECTROMECHANICAL DEVICES; MODULATION; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

ANALOG MULTIPLIERS; FLICKER NOISE; MULTIPLICATIVE LOCK-IN TECHNIQUE; NONLINEAR FEEDBACK TECHNIQUE; VIBRATION SENSOR;

MULTIPLYING CIRCUITS;

EID: 0036292255     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A novel CMOS monolithic analog multiplier with wide input dynamic range
2. An adaptive digital technique for compensating for analog quadrature modulator/demodulator impairments
3. Effects of offsets on bipolar integrated circuit mixer even-order distortion terms