A new offset measurement and cancellation technique for dynamic latches

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Al Rawi, Ghazi A ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC SWITCHES; INTEGRATED CIRCUIT LAYOUT; NAND CIRCUITS;

CMOS COMPARATOR; DYNAMIC LATCH OFF-SET MEASUREMENT TECHNIQUE; MULTISTAGE OFFSET CANCELLATION;

DIFFERENTIAL AMPLIFIERS;

EID: 0036287731     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A 100-MHz piplelined CMOS comparator
2. A 10-bit 5-Msample/s CMOS two-step flash ADC
3. Design techniques for high-speed, high-resolution comparators
4. A CMOS 8-bit high-speed A/D converter IC