An efficient genetic algorithm for slicing floorplan area optimization

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2002, Pages

  Lin, Chang Tzu ^a   Chen, De Sheng ^a   Wang, Yi Wen ^a  

^a FENG CHIA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ENCODING (SYMBOLS); GENETIC ALGORITHMS; OPTIMIZATION; VLSI CIRCUITS;

GENETIC OPERATOR; SLICING FLOORPLAN AREA OPTIMIZATION; SLICING TREES;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036287604     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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10. Using genetic algorithm for slicing floorplan area optimization in circuit design
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14. An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair
15. How good are slicing floorplans