Optimization of LNS operations for embedded signal processing applications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2002, Pages

  Paliouras, V ^a  

^a UNIVERSITY OF PATRAS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; OPTIMIZATION; TABLE LOOKUP; THEOREM PROVING;

EQUIVALENCE CRITERIA; LOGARITHMIC NUMBER SYSTEM;

DIGITAL ARITHMETIC;

EID: 0036287566     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. The sign/logarithm number system
2. Unrestricted faithful rounding is good enough for most LNS applications
3. 114 MFLOPS logarithmic number system arithmetic unit for DSP applications
4. The logarithmic number system for strength reduction in adaptive filtering
5. Low-power properties of the logarithmic number system
6. Quantization noise analysis of sign/logarithm data encoders when excited by speech or sinusoidal inputs
7. A 20 bit logarithmic number system processor
8. Interleaved memory function interpolators with application to an accurate LNS arithmetic unit