Avoiding initialization misses to the heap

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2002, Pages 183-194

  Lewis, Jarrod A ^a   Blacks, Bryan ^a   Lipasti, Mikko H ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; DATA TRANSFER; MICROPROCESSOR CHIPS; STORAGE ALLOCATION (COMPUTER);

MEMORY TRAFFIC;

CACHE MEMORY;

EID: 0036286994     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

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4. A performance study of software and hardware data prefetching schemes
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6. The detection and elimination of useless misses in multiprocessors
7. Speculative execution via address prediction and data prefetching
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9. Cache write policies and performance
10. Surpassing the TLB performance of superpages with less operating system support
11. Using the SimOS machine simulator to study complex computer systems
12. Missing the memory wall: The case for processor/memory integration
13. Segregating heap objects by reference behavior and lifetime
14. Limitation of cache prefetching on a bus-based multiprocessor
15. Hitting the memory wall: Implications of the obvious